BPM Microsystems announces that it will exhibit its award-winning 2800ISP parallel in-system device programmer in Booth at the DESIGN West conference and exhibition, scheduled to take place April 22-25, 2013 at the McEnery Convention Center in San Jose, CA.
The new 2800ISP incorporates the companys 8th Generation site technology utilizing its Vector Engine Co-Processorreg; into a custom-designed test fixture, allowing its customers to program flash architectures including eMMC, PCM and Raw NAND, plus MCUs and other device technologies on-board after reflow. In 2012, the company added support for third party functional testing, such as boundary scan, with the capability to test up to 240 pins in addition to the 960 pins available for programming.
Ideal for medium- to high-volume production, the 2800ISP is configurable and can program up to 16 devices in parallel. Like all 8th Generation programmers, the 2800ISP with BPMs Vector Engine Co-Processor is capable of achieving an amazing peak operating rate of 24Gbits per second. This solves the test bottleneck while allowing the operator to program the latest data just in time, all while attaining a very low programming cost per device.
